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fn4631 rev 5.00 page 1 of 11 november 16, 2004 fn4631 rev 5.00 november 16, 2004 hip1011a pci hot plug controller datasheet the hip1011a is the second pci hot plug voltage bus control ic from intersil. a dr op-in alternative to the widely used hip1011, the hip1011a has the same form, fit and function but additionally features an adjustable latch-off time of the mosfet switches and fault reporting. like the hip1011, the hip1011a creates a small and simple yet complete power control solution with discrete power mosfets and a few passive components. four independent supplies are controlled, +5v, +3.3, +12v, and -12v. the +12v and -12v switches are integrated. for the +5v and +3.3v supplies, overcu rrent (oc) protection is provided by sensing the voltage across external current- sense resistors. for the +12v and -12v supplies oc protection is provided internally. in addition, an on-chip reference is used to monitor the +5v, +3.3v and +12v outputs for undervoltage (uv) conditions. the pwron input controls the state of the switches. during an oc condition on any output, or a uv condition on the +5v, +3.3v or +12v outputs, a low (0v) is asserted on the fltn output and all mosfets are latched-off. the time to fltn signal going low and mosfet latch-off is determined by a single capacitor from the fltn pin to ground. this added feature allows the system os to comple te housekeeping activities in preparation for an unplanned shut down of the affected card. the fltn latch is cleared when the pwron input is toggled low again. during initial power-up of the main vcc supply (+12v), the pwron input is inhibited from turning on the switches, and the latch is hel d in the reset state until the vcc input is greater than 10v. user programmability of the overcurrent threshold, fault reporting response time, latch-off response time and turn-on slew rate is provided. a resistor connected to the ocset pin programs the oc threshold. a capacitor may be added to the fltn pin to adjust both the delay time to reporting a fault and the latch-off of the supplies after an oc or uv event. capacitors connected to the gate pins set the turn-on rate. in addition the hip1011a has also been enhanced to tolerate spurious system noise. features ? adjustable delay time for turn-off and fault reporting ? controls all pci supplies: +5v, +3.3v, +12v, -12v ? internal mosfet switches for +12v and -12v outputs ? ? p interface for on/off control and fault reporting ? adjustable overcurrent protection for all supplies ? provides fault isolation ? adjustable turn-on slew rate ? minimum parts count solution ? no charge pump ? pb-free available (rohs compliant) applications ? pci hot plug ? compactpci pinout hip1011a (soic) top view ordering information part number temp. range ( o c) package pkg. dwg. # hip1011acb 0 to 70 16 ld soic m16.15 hip1011acbza (see note) 0 to 70 16 ld soic (pb-free) m16.15 HIP1011ACB-T 0 to 70 tape and reel hip1011acbza-t (see note) 0 to 70 tape and reel (pb-free) note: intersil pb-free products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible wit h both snpb and pb-free soldering operations. intersil pb-free pr oducts are msl classified at pb-free peak reflow temperatures that mee t or exceed the pb-free requirements of ipc/jedec j std-020c. 9 10 11 12 13 14 16 15 8 7 6 5 4 3 2 1 m12vin fltn 3v5vg v cc 12vin 3visen ocset 3vs m12vo 12vg gnd 12vo m12vg 5visen 5vs pwron n o t r e c o m m e n d e d f o r n e w d e s i g n s n o r e c o m m e n d e d r e p l a c e m e n t c o n t a c t o u r t e c h n i c a l s u p p o r t ce n t e r a t 1 - 8 8 8 - i n t e rs i l o r w w w . i n t e r s i l . c o m / t s c
hip1011a fn4631 rev 5.00 page 2 of 11 november 16, 2004 typical application simplified schematic 12v, m12vin fltn 3v5vg v cc 12vin 3visen 3vs ocset m12vo 12vg gnd 12vo 5visen 5vs pwron m12vg hip1011a 3.3v, 12v input 5v, -12v, 5v input -12v input power control input 0.033 ? f 0.033 ? f 6.04k ? fault output (active low) (optional) 5m ? , 1% 0.033 ? f 1% 3.3v input 5m ? , 1% 7.6a out 0.5a out 0.1a out 5a out itf86130sk8t note: all capacitors are ?? 10%. itf86130sk8t fltn 5vs 3v5vg 5visen 3vs ocset 3visen 12vin 12vg 12vo m12vin m12vg m12vo pwron gnd 12vin power-on reset v cc m12vin v cc v cc 100 ? a 0.3 ? 0.7 ? fault latch v ocset 5v zener reference v cc 5vref 5vref v ocset /17 v ocset /0.8 4.6v inhibit v cc set (low = fault) reset v cc low = fault low when v cc < 10v high = switches on high = fault + - comp - + comp - + v ocset /13.3 + - comp + 2.9v inhibit comp + - 10.8v inhibit comp + - comp - + + - v cc v cc v ocset /3.3 comp - + + - -
hip1011a fn4631 rev 5.00 page 3 of 11 november 16, 2004 pin descriptions pin no. designator function description 1 m12vin -12v input -12v supply input. also provi des power to the -12v overcurrent circuitry. 2 fltn fault output 5v cmos fault output; low = fault. a capacitor may be placed from this pin to ground to provide delay time to fault not ification and power supply latch-off. 3 3v5vg 3.3v/5v gate output drive the gates of the 3.3v and 5v mosfets. connect a capacitor to ground to set the start- up ramp. during turn on, this capacitor is charged with a 25 ? a current source. 4vcc 12v v cc input connect to unswitched 12v supply. 5 12vin 12v input switched 12v supply input. 6 3visen 3.3v current sense connect to the load side of the current sense resistor in series wi th source of external 3.3v mosfet. 7 3vs 3.3v source connect to source of 3.3v mosfet. this connection along with pin 6 (3visen) senses the voltage drop across the sense resistor. 8 ocset overcurrent set connect a resistor from this pin to ground to set the overcurrent trip point of all four switches. all four over current trips can be programmed by changing the value of this resistor. the default (6.04k ??? 1%) is compatible with the maximum allowable currents as outlined in the pci specification. 9 pwron power on control controls all four switches. high to turn switches on, low to turn them off. 10 5vs 5v source connect to source of 5v mosfet switch. this connection along with pin 11 (5visen) senses the voltage drop across the sense resistor. 11 5visen 5v current sense connect to the load side of the current sense resistor in series with source of external 5v mosfet. 12 12vo switched 12v output switched 12v output. 13 gnd ground connect to common of power supplies. 14 12vg gate of internal pmos connect a capacitor between 12v g and 12vo to set the start up ramp for the +12v supply. this capacitor is charged with a 25 ? a current source during start-up. the uv circuitry is enabled after the voltage on 12vg is less than 400mv. therefore, if the capacitor on the pin 3 (3v5vg) is more than 25% larger than the capacitor on pin 14 (12vg) a false uv may be detected during start up. 15 m12vg gate of internal nmos connect a capacitor between m 12vg and m12vo to set the start up ramp for the m12v supply. this capacitor is charged with 25 ? a during start up. 16 m12vo switched -12v output switched 12v output.
hip1011a fn4631 rev 5.00 page 4 of 11 november 16, 2004 absolute maximum ratings thermal information v cc , 12vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +14.0v 12vo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to v 12vin +0.5v 12vo, 12vg, 3v5vg . . . . . . . . . . . . . . . . . . . . . -0.5v to v cc +0.5v m12vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15.0v to +0.5v m12vo, m12vg. . . . . . . . . . . . . . . . . . . . . . v m12vin -0.5v to +0.5v 3visen, 5visen . . . . . . . . . . . -0.5v to the lesser of v cc or +7.0v voltage, any other pin . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +7.0v 12vo output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3a m12vo output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8a esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kev (hbm) operating conditions vcc supply voltage range. . . . . . . . . . . . . . . . . . +10.8v to +13.2v ? 12v, 5v and 3.3v input supply tolerances ??????????????????????????????? ? 10% 12vo output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to +0.5a m12vo output current . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to +0.1a temperature range (t a ) . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 70 o c thermal resistance (typical, note 1) ? ja ( o c/w) soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . .125 o c maximum storage temperature range . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c (soic - lead tips only) die characteristics number of transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ? ja is measured with the component mounted on a low effective ther mal conductivity test board in free air. see tech brief 379 for details. 2. all voltages are relative to gnd, unless otherwise specified. electrical specifications nominal 5.0v and 3.3v input supply voltages, v cc = 12vin = 12v, m12vin = -12v, t a = t j = 0 to 70 o c, unless otherwise specified parameter symbol test conditions min typ max units 5v/3.3v supply control 5v overcurrent threshold i oc5v see typical application diagram - 7.1 - a 5v overcurrent threshold voltage v oc5v_1 v ocset = 0.6v 30 36 42 mv 5v overcurrent threshold voltage v oc5v_2 v ocset = 1.2v 66 72 79 mv 5v undervoltage trip threshold v 5vuv 4.42 4.65 4.75 v 5v undervoltage fault response time t 5vuv - 150 350 ns 5v turn-on time (pwron high to 5vout = 4.75v) t on5v c 3v5vg = 0.022 ? f, c 5vout = 2000 ? f, r l = 1 ? -6.5- ms 5vs input bias current ib 5vs pwron = high -40 -26 -20 ? a 5visen input bias current ib 5visen pwron = high -160 -140 -110 ? a 3v overcurrent threshold i oc3v see typical application diagram - 9.0 - a 3v overcurrent threshold voltage v oc3v_1 v ocset = 0.6v 42 49 56 mv 3v overcurrent threshold voltage v oc3v_2 v ocset = 1.2v 88 95 102 mv 3v undervoltage trip threshold v 3vuv 2.74 2.86 2.97 v 3v undervoltage fault response time t 3vuv - 150 350 ns 3v turn-on time (pwron high to 3vout = 3.00v) t on3v c 3v5vg = 0.022 ? f, c 3vout = 2000 ? f, r l = 0.43 ? -6.5- ms 3vs input bias current ib 3vs pwron = high -40 -26 -20 ? a 3visen input bias current ib 3visen pwron = high -160 -140 -110 ? a 3v5vg vout low vout_lo_35vg pwron = low, fltn = low - 0.1 0.4 v 3v5vg vout high vout_hi_35vg pwron = high, fltn = high 10.5 11.1 - v gate output charge current ic 3v5vg pwron = high, v 3v5vg = 2v 22.5 25.0 27.5 ? a
hip1011a fn4631 rev 5.00 page 5 of 11 november 16, 2004 gate turn-on time (pwron high to 3v5vg = 11v) t on3v5v c 3v5vg = 0.1 ? f - 280 500 ? s gate turn-off time t off3v5v c 3v5vg = 0.1 ? f, 3v5vg from 9.5v to 1v - 13 17 ? s gate turn-off time c 3v5vg = 0.022 ? f, 3v5vg falling 90% to 10% -2- ? s +12v supply control on resistance of internal pmos r ds(on)12 pwron = high, i d = 0.5a, t a = t j = 25 o c 0.18 0.3 0.35 ? overcurrent threshold i oc12v_1 v ocset = 0.6v 0.6 0.75 0.9 a overcurrent threshold i oc12v_2 v ocset = 1.2v 1.25 1.50 1.8 a 12v undervoltage trip threshold v 12vuv 10.5 10.8 11.15 v undervoltage fault response time t 12vuv - 150 - ns gate charge current ic 12vg pwron = high, v 12vg = 3v 23.5 25.0 28.5 ? a turn-on time (pwron high to 12vg = 1v) t on12v c 12vg = 0.022 ? f - 16 20 ms turn-off time t off12v c 12vg = 0.1 ? f, 12vg - 9 12 ? s turn-off time c 12vg = 0.022 ? f, 12vg rising 10% - 90% -3- ? s -12v supply control on resistance of internal nmos r ds(on)m12 pwron = high, i d = 0.1a, t a = t j = 25 o c 0.5 0.7 0.9 ? overcurrent threshold i oc12v_1 v ocset = 0.6v 0.15 0.18 0.25 a overcurrent threshold i oc12v_2 v ocset = 1.2v 0.30 0.37 0.50 a gate output charge current ic m12vg pwron = high, v 3vg = -4v 22.5 25 27.5 ? a turn-on time (pwron high to m12vg = -1v) t onm12v c m12vg = 0.022 ? f - 160 300 ? s turn-on time (pwron high to m12vo = -10.8v) t onm12v c m12vg = 0.022 ? f, c m12vo = 50 ? f, r l = 120 ? -16-ms turn-off time t offm12v c m12vg = 0.1 ? f, m12vg - 18 23 ? s turn-off time c m12vg = 0.022 ? f, m12vg falling 90% to 10% -3- ? s m12vin input bias current ib m12vin pwron = high - 2 2.6 ma control i/o pins supply current i vcc 455.8ma ocset current i ocset 95 100 105 ? a overcurrent to fault response time t oc fltn cap = 100pf - 500 960 ns overcurrent to fault response time fltn cap = 1000pf - 2200 - ns overcurrent to fault response time fltn cap = 10 ? f-30- ? s pwron threshold voltage v thpwron 0.8 1.6 2.1 v fltn output low voltage v fltn,ol i fltn = 2ma - 0.6 0.9 v fltn output high voltage v fltn,oh i fltn = 0 to -4ma 3.9 4.3 4.9 v fltn output latch threshold v fltn,th 1.45 1.8 2.25 v 12v power on reset threshold v por,th v cc voltage falling 9.4 10 10.6 v electrical specifications nominal 5.0v and 3.3v input supply voltages, v cc = 12vin = 12v, m12vin = -12v, t a = t j = 0 to 70 o c, unless otherwise specified (continued) parameter symbol test conditions min typ max units
hip1011a fn4631 rev 5.00 page 6 of 11 november 16, 2004 typical performance curves figure 1. r on vs temperature figure 2. uv trip vs temperature figure 3. 12 uv trip vs temperature figure 4. oc vth vs temperatur e (vr ocset = 1.21v) figure 5. ocset i vs temperature 340 320 300 280 260 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 1000 900 800 700 600 pmos r on +12 (m ? ) nmos r on -12 (m ? ) temperature ( o c) nmos -12 r on pmos +12 r on 4.632 4.631 4.630 4.629 4.626 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 5v uvtrip (v) 3.3v uvtrip (v) temperature ( o c) 5 uv 4.628 4.627 2.862 2.861 2.860 2.859 2.858 3.3 uv 10.84 10.83 10.82 10.81 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 12 uv trip (v) temperature ( o c) 100 90 80 70 60 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 oc vth (mv) temperature ( o c) 5v ocvth 3v ocvth 102 101 100 99 98 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 ioc set (ma) temperature ( o c)
hip1011a fn4631 rev 5.00 page 7 of 11 november 16, 2004 figure 6. fltn, 3v5vg response to oc, fltn = 100pf figure 7. fltn, 3v5vg response to oc, fltn cap = 0.001 ? f figure 8. fltn, 3v5vg response to oc, fltn cap = 0.01 ? f figure 9. fltn, 3v5vg response to oc, fltn cap = 1 ? f figure 10. response time vs fltn cap typical performance curves (continued) voltage (2v / div) time (1 ? s /div) current (5a / div) 5v iout 3v5vg fltn voltage (2v / div) time (1 ? s /div) current (5a / div) fltn 5v iout 3v5vg fltn voltage (2v / div) time (2 ? s /div) current (5a / div) 5v iout 3v5vg fltn voltage (2v / div) time (50 ? s /div) current (5a / div) 5v iout 3v5vg fltn 1ns 10ns 100ns 1 ? s 10 ? s 100 ? s 1ms 10ms 0.001 ? f0.1 ? f1 ? f10 ? f 100pf 0.01 ? f vg
hip1011a fn4631 rev 5.00 page 8 of 11 november 16, 2004 hip1011a pci hot plug controller key feature description and operation a drop-in alternative to the widely used hip1011, the hip1011a additionally features an adjustable delay time to fault reporting and latch-off of the mosfet switches. during an over current condition (oc) on any output, or an under voltage (uv) condition on the +5 v, +3.3v or +12v outputs, a low (0v) is presented on the fltn output and all mosfets are latched-off. a programmable delay time from an oc or uv event to the fltn signal going low and mosfet latch-off can be de signed into the system by a single capacitor from the fltn pin to ground. the addition of an increasingly larger capacitor value on the fltn pin increases the time from the oc or uv occurrence to the start of the fltn high to low transition. the capacitor also slows the falling ramp thus delaying reaching the fltn latch threshold of ~2.4v. once the fltn latch voltage threshold is reached the hip1011a then simultaneously shuts down all four supplies. this added feat ure enables the hip1011a to ignore both transient uv and oc events to the extent of a single capacitor value in t he system design. this feature also may allow the system os to complete housekeeping activities in preparation for a possible unplanned shutdown of the affected card by receiving an early warning signal from the hip1011a. customizing and optimizing circuit performance and functionality how adjustable is the f ault reporting delay and time to power supply latch-off? figure 12 illustrates the relationship between the fltn signal and the gate drive outputs. duration a , indicates the time between fltn starting to transition from high to low, (indicating a fault has occurred) and the start of the gate drive outputs latching off. the latch-off is initiated by the falling fltn signal reaching the output latch threshold voltage, v fltn, th . table 1 illustrates the effect of the fltn capacitor on the response time. can the hip1011a be used on a compactpci board? yes, the hip1011a can be used on a compactpci card application. see technical brief tb358. note: 3. all capacitors are ? 10%. figure 11. hip1011a typical application 12v m12vin fltn 3v5vg v cc 12vin 3visen 3vs ocset m12vo 12vg gnd 12vo 5visen 5vs pwron m12vg hip1011a 3.3v 12v input 5v -12v 5v input -12v input power control input 0.033 ? f 0.033 ? f 6.04k ? fault output (active low) (see table 1) 5m ? 1% 0.033 ? f 1% 3.3v input 5m ? 1% 7.6a out 0.5a out 0.1a out 5a out table 1. response time table 0.001 ? f0.1 ? f10 ? f 3v5vg response a 0.85 ? s37 ? s3.8ms 3v5vg fltn a t1 t2 figure 12. timing diagram v fltn, th
hip1011a fn4631 rev 5.00 page 9 of 11 november 16, 2004 are there pcb layout d esign best practices to follow? what are they? as with most innovative ics performing critical tasks there are crucial pcb layout best practices to follow for optimal performance. pcb traces that connect each end of the current sense resistors to t he hip1011a must not carry any load current. this can be accomplished by two dedicated pcb traces directly from the s ense resistor to the hip1011a, see examples of correct and incorrect layouts in figure 13. typical applications : hip1011a pci hot plug controller introduction to hip1011a and pci hot plug evaluation board the hip1011a is compatible with the pci hot plug specification as it is derived from the widely used hip1011. this device facilitates ?hot plugging?, the removal or insertion of pci compliant cards without the need to power down the server voltage bus. the hip1011a controls all four, -12v, +12v, +3.3v, +5v supplies found in pci applications, monitoring and pr otecting all against over current (oc) and the +12v, +3 .3v, +5v for under voltage (uv) conditions. reference the pci hot plug specification available from www.pcisig.com. figure 14 illustrates the pcb pattern for implementation of the hip1011a with 4 power mosfets. additional components for optimizing performance in particular applications, ambient electrical noise levels or desired features will be necessary. t he ease of implementation of the hip1011a and mosfets is complemented by the small pcb foot print necessary, since both are available in 0.150 inch soics. the typical application requires only 1.1 square inches of pcb board space. is there a hip1011a pc i hot plug evaluation board available? there is an evaluation board av ailable through your local intersil sales office. the hip1011aeval1 board (figure 15) is a simple board designed to demonstrate and evaluate the hip1011a using an external pwron signal simulating a pci hot plug environment. the hip1011aeval1 board comes in 2 parts, the mother board with the hip1011a, mosfets with external components and a load board simulating a ?typical? pci load with adequate space for modifying the existing load or to add an electronic load. even with a number of available test points the hip1011a implementation space is still ve ry efficient. in addition, the demo board offers adequate space to evaluate the application note discussions found in an9737. correct to hip1011a vs and visen to hip1011a vs and visen current sense resistor incorrect figure 13. sense resistor layout figure 14. layout plot, actual size (0.75in x 1.5in) 1.5in 0.75in
hip1011a fn4631 rev 5.00 page 10 of 11 november 16, 2004 q1, q2 -12vout c2 q3, q4 r3 c3 r4 c4 c1 indicates edge connector socket rl1 load board indicates edge connector card cl1 figure 15. hip1011aeval1 table 2 details the bom for the hip1011aeval1 board. m12vin fltn 3v5vg v cc 12vin 3visen 3vs ocset m12vo 12vg gnd 12vo 5visen 5vs pwron m12vg hip1011a 12v input 5v input -12v input r1 3.3v input r2 5vout 12vout 3.3vout gnd 5v 3.3v rl2 cl2 5.0v rl3 cl3 +12v rl4 cl4 -12v bus board d1 indicates banana jacks v cc pwron in 6 jp2 3, 4, 5 tp8 2 tp6 1 tp7 9, 11, 12 tp5 7, 8, 10 tp9 jp1 tp11 tp4 tp1 tp2 tp3 tp10 table 2. component designator component name component description u1 hip1011acb pci hot plug controller intersil corporation, hip1011acb pci hot plug controller q1, q2, q3, q4 rf1k49211 intersil corporation, rf1k49211 7a, 12v, 20m ? , logic level n-channel mosfet r1, r2 r sense for 3.3v and 5v supplies dale, wsl-2512 10m ? metal strip resistor c1, c2, c3 gate timing capacitors 0.033 ? f 805 chip capacitor r3 over current set resistor 12.1k ? 805 chip resistor c4 fault stability capacitor 100pf 805 chip cap conn. 1 connector for load card sullins ezm06drxh r4 led series resistor 4.7k ? 805 chip resistor d1 fault indicating led red led jp1 v cc to switched or unswitched 12v supply 0.01? spaced pins for jumper block jp2 pwron to 5v 0.01? spaced pins for jumper block rl1 3.3v load board resistor 1.1 ? , 10w rl2 5.0v load board resistor 2.5 ? , 10w rl3 +12v load board resistor 47 ? , 5w rl4 -12v load board resistor 240 ? , 2w cl1, cl2 +3.3v and +5.0v load board capacitor 2200 ? f cl3, cl4 +12v and -12v load board capacitor 100 ? f
fn4631 rev 5.00 page 11 of 11 november 16, 2004 hip1011a intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas ll c 2000-2004. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interlead flash or protrusions. in- terlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimen- sions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m b s e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m ? m16.15 (jedec ms-012-ac issue c) 16 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.053 0.069 1.35 1.75 - a1 0.004 0.010 0.10 0.25 - b 0.014 0.019 0.35 0.49 9 c 0.007 0.010 0.19 0.25 - d 0.386 0.394 9.80 10.00 3 e 0.150 0.157 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.228 0.244 5.80 6.20 - h 0.010 0.020 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n16 167 ? 0 o 8 o 0 o 8 o - rev. 1 02/02

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